A static random access memory (SRAM) cell includes cross-coupled inverters configured to form a storage node and a complementary storage node, and pass gates to control access of the storage nodes, respectively. The pass gates are controlled by a word line and are configured to couple the storage node and the complementary storage node to a bit line and a complementary bit line, respectively, when the word line is asserted.
In some approaches, during a read operation of the SRAM cell, the word line is asserted, and based on data stored at the storage node and the complementary storage node, one of the bit line and complementary bit line discharges through the corresponding inverter for data sensing. During a write operation of the SRAM cell, the discharge of the bit line or complementary bit line is arranged to cause the voltage at the corresponding storage node to exceed the switching threshold of the inverter driven by the storage node to flip the stored data. When the read operation or the write operation is performed on the SRAM cell, each of other SRAM cells in the same row also experience a dummy read operation because the asserted word line also drives pass gates of each of the other SRAM cells.
Like reference symbols in the various drawings indicate like elements.